Tag Archives: IP

5G, News

AccelerComm to Demonstrate How Spectral Efficiency is Key to 5G Small Cell Success at SCWS 2022

Company to present critical role of its physical layer IP solutions in maximising performance of dense networks at Small Cell Forum’s flagship event

London, UK – May 19th 2022 – AccelerComm, the Layer 1 5G IP specialists, today announced that it will be presenting a range of its solutions that help maximise the performance of 5G small cells at the SCWS 2022 event in London from May 24th-25th. The company provides 5G physical layer IP solutions which enable optimal performance of small cell 5G radio networks by mitigating the effects of noise, interference, and poor signal strength, thereby increasing throughput, reducing latency, and maximising spectral efficiency.

The gains available from deploying the complete AccelerComm solution are considerable, enabling operators to as much as double the capacity of their spectrum, resulting in up to a 30% reduction in CAPEX spending on infrastructure. This not only helps make the business case for 5G more compelling, but will also enable a range of new applications and services though higher performance, reliability and lower latency.

As SCWS, AccelerComm will be presenting three key benefits of its physical layer IP solutions for small cells:

  • Doubling of spectral efficiency: The AccelerComm channel equaliser can as much as double the average cell spectral efficiency, which in turn brings an improvement in network performance and results in a large potential reduction in the required number of sites (and hence power) required to provide coverage.
  • Higher throughputs: Look-aside FPGA-based Accelerator with 16 Gbps of throughput using the O-RAN Acceleration Abstraction Layer (AAL) interface.
  • Reduced LDPC Block error rates for improved URLLC performance: LDPC Block error rates using a Xilinx T2 Telco Card deliver improved BLER performance, enabling increased receiver gain, s and no error floors which is important for URLLC applications.

To learn more contact: info@accelercomm.com

To arrange a meeting please visit: Small Cells World Summit 2022 | AccelerComm

Electronics, News

Codasip adopts Siemens’ OneSpin tools for formal verification

Higher-quality verification to drive adoption and build momentum for RISC-V IP

Munich, 3 May 2022 – Codasip, the leader in processor design automation, has expanded its adoption of formal verification solutions for comprehensive and thorough processor testing with the addition of OneSpin IC verification tools from Siemens EDA. Codasip has continually invested heavily in processor verification to underpin the company’s ability to deliver the industry’s highest quality RISC-V processor IP.

Siemens EDA’s OneSpin tools provide an advanced and incredibly robust verification platform to tackle critical IC integrity issues. The highly advanced OneSpin formal verification tools for automotive and other high-integrity processor applications verify the implementation with minimal set up and runtime.

The quality of Codasip RISC-V processor IP sets it apart from competitors. With 2 billion cores of Codasip processor IP already in use, mostly with tier one customers, it is essential that Codasip continues to offer processor IP that is consistently of the highest quality

Neil Hand, strategy director for the IC Design Verification division of Siemens EDA, “We are pleased to collaborate with Codasip to help ensure the high quality of their RISC-V Processor IP, as well as to establish optimized solutions for our mutual customers. The world-class technology of our OneSpin formal verification tools including the OneSpin RISC-V verification solution, together with Codasip’s innovative RISC-V IP, is key for IC designers to deliver high-quality products to market quickly.”

Rupert Baines, CMO, Codasip, commented, “The poor verification of some RISC-V IP is frankly shocking. Developers have legitimate concerns about the quality of RISC-V IP that’s holding back its adoption. Higher quality and formally proven RISC-V IP will help it to cross the chasm and massively increase its adoption.”

Codasip’s Director of Verification, Philippe Luc, added, “We are very proud of our own rigorous approach to verification with a strong in-house verification team – our own extremely thorough internal testing methodologies, combine with best-in-class third-party tools. As part of this, we’re delighted to use OneSpin technology from Siemens EDA, which is a key partner for Codasip – we look forward to a closer and productive relationship.”

Codasip uses Siemens EDA (formerly Mentor Graphics) as its primary EDA tool flow.

Codasip is presenting on its experiences with the OneSpin tool at Siemens EDA User2User2022 conference at Santa Clara on May 4th and in Munich on May 12th.

Automotive, News

Codasip appoints Jaime Broome as its Automotive VP

Codasip presents car makers with a breakthrough in innovation and ownership of differentiation

Munich, Germany – 21 April 2022 — Codasip, the leader in customizable RISC-V processor IP, today announced it has appointed Jaime Broome as its new VP Automotive. Broome brings over 20 years of experience in semiconductors and complex IP, SoCs and the automotive supply chain, having recently led Imagination Technologies’ Automotive Business unit dealing with the entire industry, from manufacturers to tier 1 suppliers and ecosystem partners.

Broome brings significant experience of the ecosystem, industry contacts, as well as strategic insights into the market, technology innovations, opportunities, and the trends – all of which are ideally suited to Codasip’s technology and its ability to support and enable exactly the innovation the industry needs in 2022. The automotive market is arguably the hottest market today for developments in electronics and semiconductors. In the face of growing competition from new tech giants the ability to differentiate in this market is the key to success, or even survival.

Broome explains, “There are some rapid shifts taking place in the car market – a new marketplace forming in automotive innovation and technology, with a battleground between existing pillars, technology giants and new businesses and business models. The companies in this market are big and small, new and old, but all are crying out for what RISC-V is offering: the ability to easily innovate rapidly at the design level by reducing the complexity, cost and speed.

“Where Codasip stands out, is that we provide the access to rapid innovation, ownership of the ability to Design for Differentiation, and cost reduction. We deliver that straight into the hands of the players experiencing the pains from the entry of new tech giants into the market. Additionally, being centered in Europe, we are best placed to avoid geopolitical ‘challenges’ and we are surrounded by the world’s greatest concentration of automotive innovators and manufacturing giants.”

In Europe, Broome joins forces with Codasip European VP, Emmanuel Till-Vattier and recently appointed VP Functional Safety (FuSa) Dave Higham, both recent recruits from Imagination. Drawing on Higham’s significant experience, the team will ensure Codasip delivers on the automotive industry’s need for rapid innovation while ensuring technology never compromises the safety or security of vehicles and passengers.

Ron Black, CEO, Codasip, added, “Having known and worked with Jamie for many years, I was delighted he was keen to join the team at Codasip: I could see how his skills and experience will enable us to tap into the full potential of Codasip technology to increase the pace of innovation in the automotive supply chain, as well as enabling innovations in electrification; and safe and secure applications for connected and autonomous vehicles”.